Conventional static random access memory cells are constructed with n-channel pass gate transistors activated by address lines. The n-channel pass gate transistors drive n-channel driver transistors and p-channel transistors within the memory cell. To achieve high speed with low power read/write operation, the gate width of the pass gate transistors is typically about one-third that of the driver transistors and the gate width of the p-channel transistors are the same as or smaller than the gate width of the pass gate transistors. Such size configurations achieve high speed with low power read/write operation and allow the memory cell to perform data write operation properly.
In gate array devices, however, there is no control over the size of particular transistors and the circuit designer must make due with the transistors available. The transistors in a gate array device are of approximately the same size to maintain signal rise and fall times as equal as possible. Similar size base cell transistors within a gate array make static random access memory cell design difficult. It is therefore desirable to have a static random access memory in a gate array device that overcomes the size limitations of the available transistors.
From the foregoing, it may be appreciated that a need has arisen to provide a static random access memory cell for a gate array device that optimally performs despite the similarly sized base cell transistors in the gate array. A need has also arisen to provide a static random access memory cell for a gate array device that effectively reduces transistor sizes to enhance performance of the memory cell.